1. Technical Field
Various embodiments relate generally to a method of manufacturing a semiconductor integrated circuit device.
2. Related Art
A highly integrated semiconductor integrated circuit device may employ a vertical transistor for integrating more memory cells in a small area.
Generally, the vertical transistor may include a gate, a source and a drain. The vertical transistor may include a channel vertically extended from an upper or top surface of a semiconductor substrate. The vertical transistor may include an active region having a pillar shape.
The gate may be configured to surround the pillar. The source may be formed in a portion of the pillar under the gate. The drain may be formed in a portion of the pillar over the gate. The channel of the vertical transistor may be formed in a portion of the pillar between the source and the drain.
However, the pillar channel of the vertical transistor may be floated differently from a channel of a planar type metal-oxide-semiconductor (MOS) transistor and may be more prone to a leakage current.
Particularly, when a voltage is applied to the gate and the drain with a gate insulating layer, a high electric field may be concentrated on an edge portion of the gate, i.e., an overlapped portion between the gate and the drain to generate a gate induced drain leakage (GIDL). The GIDL may be more pronounced in the floated channel.